Typical integrated memory devices include arrays of memory cells arranged in rows and columns. In many such memory devices, several redundant rows and columns are provided to replace malfunctioning memory cells found during testing. Testing is typically performed by having predetermined data values written to selected row and column addresses that correspond to memory cells. The memory cells are then read to determine if the data read matches the data written to those memory cells. If the read data does not match the written data, then those memory cells are likely to contain defects which will prevent proper operation of the memory device.
The defective memory cells may be replaced by remapping the memory addresses corresponding to a portion of main memory including the defective memory cells to redundant memory. A malfunctioning memory cell in a column or a row is substituted with a corresponding redundant element, such as an entire column or row of redundant memory cells, respectively. Therefore, a memory device need not be discarded even though it contains defective memory cells. Substitution of one of the redundant rows or columns is typically accomplished in a memory device by programming a specific combination of fuses, or if the memory device uses antifuses, by programming a specific combination of antifuses, located in one of several fuse or antifuse circuits in the memory device with memory address information identifying the portion of memory remapped to redundant memory.
When a row or column address received by the memory device matches one of the programmed addresses, the redundant element associated with the matching address is accessed instead of the row or column having the defective memory cells. In determining whether an address received by the memory device matches one of the programmed addresses, each incoming address is compared to the memory addresses programmed in the fuse or antifuse circuits. If a match is detected, then the corresponding redundant row or column is accessed, and the defective row or column is ignored, thus, remapping the memory address to the redundant element.
As previously discussed, memory addresses corresponding to defective memory are remapped to redundant memory. The redundant memory being arranged in replacement units, which is the smallest arrangement of redundant memory that can be used to correct a defect. For defects that affect more memory than included in a replacement unit, multiple replacement units are used to repair the defect. Conversely, where a defect affects a small number of memory cells, an entire replacement unit is used nevertheless. For example, in a memory having a replacement unit of four columns, a single bit failure is repaired by remapping memory addresses for four columns of main memory which include the single bit failure to the four columns of a replacement unit of redundant memory, even though only one memory cell is defective. A memory device can be designed with smaller replacement units to improve efficient use of redundant memory. However, where the replacement unit is smaller, such as one column of memory, the number of fuses or antifuses necessary to remap the memory addresses for a large block of defects to each one of the column replacement units may be significant since each replacement unit to which a memory address of main memory is remapped is associated with antifuses that are programmed with the remapped memory address. As a result, having more (smaller) replacement units means having more antifuses. Having the necessary number of fuses or antifuses, as well as the necessary reading and decoding circuitry to utilize the redundant memory, may consume a relatively significant amount of space on a semiconductor substrate on which the memory is formed.
Additionally, redundant memory may be arranged to replace defective memory of only a respective section of the memory array. That is, each memory section of a memory array may include a certain number of replacement units that can be used to repair defective memory located only in the respective memory section. When the redundant memory associated with a section has been exhausted, but additional defects in the memory section are still present, the memory cannot be fully repaired even if there is unused redundant memory associated with another section. As a result, it may be not be possible to fully repair a memory array under certain arrangements of defects although the total number of defective memory is less than the total number of redundant memory available. That is, the locations of the defects in combination with the number of defects can create a situation that may not be repairable due to the particular design of the redundant memory (e.g., size and arrangement of replacement units, association of replacement units to particular groups of memory).
Therefore, there is a need for a redundant memory design that is flexible and provides efficient repair of defective memory in a memory array.